1. Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly, to a delay stage and a delay circuit.
2. Discussion of the Related Art
In semiconductor integrated circuits, a delay circuit is often used to delay a signal for a predetermined period of time for the purpose of timing control, and especially, a delay circuit, which is capable of providing a constant delay irrespective of variations in operating voltage.
In conventional semiconductor circuits, internal operating voltages are used to control delay circuits. These internal operating voltages are lower than external operating voltages and are generated by internal operating voltage generating circuits in. Such a conventional approach is difficult to be applied to recently developed semiconductor integrated circuits whose external operating voltages generally have been decreased to 1.8 volts. The level of internal operating voltages are even lower than the level of the external operating voltages.
FIG. 1 is a circuit diagram illustrating a conventional delay circuit.
The conventional delay circuit shown in FIG. 1 includes a plurality of inverting delay stages 11 through 1n connected in series. Each of the inverting delay stages 11 through 1n includes an inverter IV, a P-channel metal oxide semiconductor (PMOS) capacitor CP, an N-channel metal oxide semiconductor (NMOS) capacitor CN, a PMOS transistor PM having a gate to which a ground voltage VSS is applied, and an NMOS transistor NM having a gate to which an operating voltage VCC is applied.
In the conventional delay circuit, the NMOS transistor NM changes an effective capacitance of the NMOS capacitor CN according to the operating voltage VCC, such that the delay circuit becomes insensitive to the operating voltage VCC. However, the delay time in the conventional delay circuit varies according to the time intervals between the pulses of an input signal IN.
In particular, an A node is charged with an operating voltage VCC while the input signal IN is at a “high” level, then is quickly discharged when the input signal IN is transited from a “high” level to a “low” level, and is very slowly discharged when a voltage Vgs between a gate and a source of the PMOS transistor PM approaches a threshold voltage Vtp of the PMOS transistor PM. The A node is quickly charged with remaining charges when a subsequent input signal IN is quickly transited to a “high” level. On the other hand, when the subsequent input signal IN is slowly transited to a “high” level, that is, when the subsequent “high” transition occurs after the A node is sufficiently discharged, the A node should be charged with a large amount of charges, and accordingly the A node is slowly charged.
A B node is discharged to a ground voltage VSS while the input signal IN is at a “high” level, then is quickly charged up to an operating voltage VCC minus a threshold voltage Vtn of the NMOS transistor when the input signal IN is transited from a “high” level to a “low” level, and is slowly discharged due to a sub threshold current after that. Thus, when a subsequent input signal IN is quickly transited to a “high” level, only charges corresponding to the operating voltage VCC minus the threshold voltage Vtn are discharged to the ground voltage VSS. However, when the subsequent input signal is transited to a “high” level after the B node is sufficiently charged to the maximum operating voltage VCC level, all charges corresponding to the operating voltage VCC are discharged to the ground voltage VSS, leading to an increase in delay time.
As a consequence, the conventional delay circuit has a delay time which varies according to the time intervals between pulses of the input signal IN. A need therefore exists for a delay stage and a delay circuit that is insensitive to an operating voltage and has a constant delay time irrespective of the time intervals between input signal pulses.